74LV4040 Datasheet | Philips Semiconductors

FEATURES - Optimized for Low Voltage applications: 1.0 to 5.5V - Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V - Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, - Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, - Frequency dividing circuits - Time delay circuits - Control counters - Output capability: standard - ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER Propagation delay CP to Q0 Qn to Qn+1 MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV4040 is a low- voltage Si- gate CMOS device and is pin and function patible with 74HC/HCT4040. The 74LV4040 is a 12-stage binary ripple counter with a click input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0 to Q11). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. CONDITIONS CL = 15p F VCC = 3.3V TYPICAL 12 7 16 100 3.5 UNIT t PHL/t PLH fmax CI CPD ns MHz p F p F Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in p F; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE - 40°C to +125°C - 40°C to +125°C - 40°C to +125°C - 40°C to +125°C OUTSIDE NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040 PW NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1 1998 Jun 23 853-2075 19619 Philips Semiconductors Product specification 12-stage...