74LVC169 Datasheet | Philips Semiconductors

FEATURES - Wide supply voltage range of 1.2 V to 3.6 V - In accordance with JEDEC standard no. 8-1A - Inputs accept voltages up to 5.5 V - CMOS low power consumption - Direct interface with TTL levels - Synchronous counting and loading - Up/down counting - Modular 16 binary counter - Two count enable inputs for n-bit cascading - Built-in lookahead carry capability - Presettable for programmable operation - Positive-edge triggered clock DESCRIPTION The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS patible TTL families. The 74LVC169 is a synchronous presettable binary counter which features an internal lookahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The lookahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately...