P5Z22V10 Datasheet | Philips Semiconductors

FEATURES - Industry’s first Total CMOS™ 22V10 - both CMOS design and process technologies - Fast Zero Power (FZP™) design technique provides ultra-low power and high speed - Static current of less than 75µA - Dynamic current 1/10 to 1/1000 that of peting devices - Pin-to-pin delay of only 7.5ns - Programmable output polarity - Synchronous preset/asynchronous reset capability - Security bit prevents unauthorized access - Electronic signature for identification - Design entry and verification using industry standard CAE tools - Reprogrammable using industry standard device programmers DESCRIPTION The P5Z22V10 is the first SPLD to bine high performance with low power, without the need for “turbo bits” or other power down schemes. To achieve this, Philips Semiconductors has used their FZP™ design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the bination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Philips Semiconductors offers the P3Z22V10 that offers high speed and low power in a 3V implementation. The P5Z22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an “Output Macro Cell” (OMC), which can be individually configured as a dedicated input, a binatorial output, or a registered output with internal feedback. - True Zero Power device with no turbo bits or power down schemes - Function/JEDEC map patible with Bipolar UVCMOS EECMOS 22V10s - Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP) - 24-pin TSSOP- uses 93% less in-system space than a 28-pin PLCC - 24-pin SOL - 28-pin PLCC with standard JEDEC pin-out - Available in mercial and...