SA1638BE Datasheet | Philips Semiconductors

DESCRIPTION The SA1638 is a bined Rx and Tx IF I/Q circuit. The receive path contains an IF amplifier, a pair of quadrature down-mixers, and a pair of baseband filters and amplifiers. A second pair of mixers in the transmit path transposes a quadrature baseband input up to the IF frequency. An external VCO signal is divided down internally and buffered to provide quadrature local oscillator signals for the mixers. A further divider chain, reference divider and phase detector are provided to avoid the need for an external IF synthesizer. Rx or Tx path or the entire circuit may be powered down by logic inputs. On-board voltage regulators are provided to allow direct connection to a battery supply. - High performance on-board integrated receive filters with bandwidth tunable between 50-850 k Hz - Switchable alternative bandwidth setting available to allow channel bandwidth flexibility in operation - Designed for a widely used I and Q baseband GSM interface - Control registers power up in a default state - Optional DC offset trim capability to <200m V - Only a standard reference input frequency required, choice of 13, 26, 39 or 52MHz FEATURES - Fully patible with SA1620 GSM RF front-end (see Figure 9) APPLICATIONS - Direct supply: 3.3V to 7.5V - Two DC regulators giving 3.0V output - Low current consumption: 18m A for Rx or 22m A for Tx - Input/output IF frequency from 70-400 MHz - Internal IF PLL for synthesizing the local oscillator signal PIN CONFIGURATION - IF circuitry for GSM 900MHz hand-held units - IF circuitry for PCN (DCS1800) hand-held units - Quadrature up and down mixer stage LQFP Package GNDREG1 Tx IFOUTX Tx IFOUT Rx IF INX Vcc Tx Rx PONPLL Rx IF IN Vcc CP GND1 GND2 GND3 48 47 46 45 44 43 42 VREG1 VREGF2 VREG2 GNDREG2 PON VBATT AOUT BOUT DCRES RESD RESA RESB 1 2 3 4 5 6 7 8 9 10 11 12 41 40 39 38 37 36 35 34 33 32 31 VEECP IREF LO INX LO IN ADJ IN CLK IN CLK INX LOCK STROBE CLOCK DATA VEEDIG 48- pin LQFP CP 30 29 28 27 26 25 Vcc DIG 13 14 15 16 17 18 19...