SAA4952WP Description
The memory controller SAA4952WP is the improved version of the SAA4951WP. The circuit has been designed for high-end TV sets using 2fH technics.
SAA4952WP Key Features
- Support for acquisition, display and deflection PLL
- 50/100 Hz (or 60/120 Hz) scan conversion
- Progressive scan 50 Hz/1250 lines (60 Hz/1050 lines) interlaced or 50 Hz/625 lines (60 Hz/525 lines) non-interlaced in s
- 50 Hz/625 lines (60 Hz/525 lines) mode support for a PALplus system and basic features
- Configured as a three clock system with a fixed 27 MHz deflection clock (deflection controlled by the TDA9151)
- Configured as a two-clock system (deflection controlled by e.g. TDA9152)
- Single clock for 50 Hz vertical and 15.625 kHz horizontal frequency
- Support of new IC generations [PAN-IC (SAA4995WP), VERIC (SAA4997H), MACPACIC (SAA4996H) and LIMERIC (SAA4945H)]
- Support for two or one field memories
- Still picture