Pixelplus PC3030K
1/3.7 inch NTSC/PAL CMOS Image Sensor
FEATURES
- [Fig. 1] PINDESCRIPTION
- [Table 1] Typical Parameters ▶ Pin Descriptions - [Table 2] Pin Descriptions ▶ Signal Environment ▶ Chip Architecture - [Fig. 2] Block Diagram ▶ Frame Structure and Windowing - [Fig. 3] Def ault data structure of f rame and window ▶ Data Formats - [Fig. 4] Bayer Color Filter Pattern - [Fig. 5] 4:2:2 YUV Data Sequence. ▶ Data and Synchronization Timing 1) VGA - [Fig. 6] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( YUV mode : def ault ) - [Fig. 7] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( Bayer mode) - [Fig. 8] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( RGB565 mode ) - [Fig. 9] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( RGB444 mode ) 2) ITU-R BT656 - [Fig. 10] Timing Diagram of ITU-R BT601 and ITU-R BT656. - [Fig. 11] Vertical Timing Diagram of ITU-R of ITU-R BT656. ▶ Scaling - [Fig. 12] Free Scaling - [Fig. 13] Ef f ective Image Size - [Fig. 14] Timing Diagram f or Full Mode - [Fig. 15] Timing Diagram f or XY-Scaling Mode ▶ Wire-strapping - [Fig.