PO74G00A Datasheet | Potatosemi

FEATURES : . Patented technology . Specified From - 40°C to 85°C, - 40°C to 125°C, and - 55°C to 125°C . Operating frequency up to 1.125GHz with 2pf load . Operating frequency up to 750MHz with 5pf load .. . Operating frequency up to 350MHz with 15pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 1.5ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 m A Per JESD 17 . ESD Protection Exceeds JESD 22 . 2000-VHuman-Body Model (A114-A) . 200-VMachine Model (A115-A) . 1000-VCharged-Device Model (C101) . Available in 14pin 150mil wide SOIC package . Available in 14pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier 09/12/07 DESCRIPTION : Potato Semiconductor’s PO74G00A is designed for world top performance using submicron CMOS technology to achieve 1.125GHz TTL/CMOS output frequency with less than 1.5ns propagation delay. This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The PO74G00A performs the Boolean function Y= A - B or Y= A + B in positive logic. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Pin Configuration 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 V CC 4B 4A 4Y 3B 3A 3Y 1Y NC 2A NC 2B 1B 1A NC VCC 4B 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4A NC 4Y NC 3B Pin Description INPUTS A H L X B H X L OUTPUT Y L H H Logic Block Diagram Copyright © 2005-2007, Potato Semiconductor Corporation 2Y GND NC 3Y 3A PO54G00A, PO74G00A QUADRUPLE 2-INPUT POSITIVE-NAND GATE 54, 74 Series GHz Logic 09/12/07 Maximum Ratings Description Storage Temperature .. Max -65 to 150 -55 to 125 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other...