A2S56D30CTP Overview
All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strob , and output data and data strobe are referenced on both edges of CLK. The A2S56D20/30/40 CTP achieves very high speed clock rate up to 200 MHz.
A2S56D30CTP Key Features
- Double data rate architecture ; two data transfers per clock cycle
- Bidirectional , data strob (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- mands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency
- 2.0 / 2.5/ 3 (programmable) ; Burst length
- 2 / 4 / 8 (programmable) Burst type