A2S56D40CTP - 256Mb DDR SDRAM

Product Overview

Powerchip Semiconductor

Datasheet Details

Part number	A2S56D40CTP
Manufacturer	Powerchip Semiconductor
File Size	620.59 KB
Description	256Mb DDR SDRAM
Datasheet	A2S56D40CTP Datasheet
Additional preview pages of the A2S56D40CTP datasheet.

Product details

Description

A2S56D30CTP is a 4-bank x 8,388,608-word x 8bit, A2S56D40CTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

- Vdd=Vddq=2.5V ± 0.2V power supply for -6,-75. -Vdd=Vddq=2.6V ± 0.1V power supply for -5. - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strob (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address).

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Other Datasheets by Powerchip Semiconductor

A2S56D20CTP - 256Mb DDR SDRAM
A2S56D30CTP - 256Mb DDR SDRAM

Published: Jul 22, 2010 |