A3S12D30ETP Overview
All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The A3S12D30/40ETP achieves very high speed data rate up to 200MHz, and are suitable for main memory in puter systems.
A3S12D30ETP Key Features
- Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5)
- Vdd=Vddq=2.6V+0.1V (for speed grade -5)
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- mands entered on each positive CLK edge
- data and data mask referenced to both edges of DQS
- Four internal banks for concurrent opertation
- 4 bank operation controlled by BA0, BA1 (Bank Address)