A3S12D40ETP Datasheet PDF - Powerchip 512Mb DDR SDRAM Specs

A3S12D40ETP - 512Mb DDR SDRAM

This page provides the datasheet information for the A3S12D40ETP, a member of the A3S12D30ETP 512Mb DDR SDRAM family.

Datasheet Summary

Description

A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

- Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5) - Vdd=Vddq=2.6V+0.1V (for speed grade -5) - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - Four internal banks for concurrent opertation - 4 bank opera.

Datasheet Details

Part number	A3S12D40ETP
Manufacturer	Powerchip
File Size	2.10 MB
Description	512Mb DDR SDRAM
Datasheet	A3S12D40ETP Datasheet
Additional preview pages of the A3S12D40ETP datasheet.

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Full PDF Text Transcription

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512Mb DDR SDRAM Specification A3S12D30ETP A3S12D40ETP Powerchip Semiconductor Corp. No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu Taiwan, R.O.C. TEL:886-3-5795000 FAX:886-3-5792168 Free Datasheet http://www.datasheet4u.net/ Powerchip Semiconductor Corporation A3S12D30/40ETP 512Mb DDR Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK.

Published: Feb 4, 2014 |