P25C128F Datasheet | Puya Semiconductor

Description The P25C128F is Serial Peripheral Interface (SPI) patible EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 128 Kbits (16 Kbytes), which is organized in 64 bytes per page. Features - Single supply voltage: 1.65 V to 3.6 V - Max clock frequency: 5 MHz - Serial Peripheral Interface (SPI) patible - Standard SPI: C, S#, D, Q, W#, HOLD# - Memory array - 128 Kbits of EEPROM - Page size: 64 bytes - Write - Byte/Page Write within 5ms - Additional Write lockable page (Identification Page) - Additional 128 bits Serial Number (Unique ID) - Hardware Controlled Locking of Protected Sectors by WP Pin - Transparent ECC on each group of four bytes which can correct 1-bit error - Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years - Package: SOP8 (150 mil/ 208 mil), TSSOP8, UDFN8, WLCSP8 1/34 1. Pin Configuration 1.1 Pin Configuration P25C128F Datasheet Rev. 1.3 S# 8 Vcc 2 7 HOLD# W# 3 6 C Vss 4 5 D S# 1 Q2 W# 3 Vss 4 8 Vcc 7 HOLD# 6C 5D SOP8/TSSOP8/UDFN8 WLCSP8 1.2 Pin Definition Table 1-1 SOP8/TSSOP8/UDFN8 Pin Definition for...