P25C256F Datasheet | Puya Semiconductor

Description The P25C256F is Serial Peripheral Interface (SPI) patible EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 256 Kbits (32 Kbytes), which is organized in 64 bytes per page. Features - Single supply voltage: 1.65 V to 3.6 V - Max clock frequency: 5 MHz - Serial Peripheral Interface (SPI) patible - Standard SPI: C, S#, D, Q, W#, HOLD# - Write - Byte/Page Write within 5ms - Additional Write lockable page (Identification Page) - Additional 128 bits Serial Number (Unique ID) - Hardware Controlled Locking of Protected Sectors by WP Pin - Transparent ECC on each group of four bytes which can correct 1-bit error - Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years - Package: PDIP8, SOP8(150mil/208mil), MSOP8, TSSOP8, UDFN8 and WLCSP8 1/36 1. Pin Configuration 1.1 Pin Configuration Figure 1-1 Pin Configuration P25C256F Datasheet Rev.1.3 S# 1 8 Vcc 2 7 HOLD# W# 3 6 C Vss 4 5 D PDIP8/SOP8(150mil/208mil)/MSOP8/TSSOP8/UDFN8 TOP VIEW BOTTOM VIEW WLCSP8 1.2 Pin Definition Table 1-1 Pin Definition for Package SOP8 Pin Name Type S#...