P25D40SH Datasheet | Puya Semiconductor

Overview General - Single 2.3V to 3.60V supply - Industrial Temperature Range 0C to 70C - Serial Peripheral Interface (SPI) patible: Mode 0 and Mode 3 - Single, Dual IO mode - 4M x 1 bit - 2M x 2 bits - Flexible Architecture for Code and Data Storage - Uniform 256-byte Page Program - Uniform 256-byte Page Erase - Uniform 4K-byte Sector Erase - Uniform 32K/64K-byte Block Erase - Full Chip Erase - Hardware Controlled Locking of Protected Sectors by WP Pin - One Time Programmable (OTP) Security Register - 3- 512-Byte Security Registers With OTP Lock - 128 bit unique ID for each device - Fast Program and Erase Speed - 2ms Single/Dual Page(s) program time - 16ms Page erase time - 16ms 4K-byte sector erase time - 16ms 32K/64K-byte block erase time - JEDEC Standard Manufacturer and Device ID Read Methodology - Ultra-Low Power Consumption - 0.6u A Deep Power Down current - 10.0u A Standby current - 2.0m A Active Read current at 33MHz - 2.5m A Active Program or Erase current - High Reliability - 100,000 Program / Erase Cycles - 10-year Data Retention - Industry Standard Green Package Options - 8-pin SOP (150mil) - 8-land USON (3x2x0.55mm) - KGD for Si P P25D40SH...