PY25Q40HB Datasheet | Puya Semiconductor

Overview General - Single 2.3 to 3.6V supply - Serial Peripheral Interface (SPI) patible: Mode 0 and Mode 3 - Single, Dual, Quad SPI, QPI - Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - QPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Flexible Architecture for Code and Data Storage - Uniform 256-byte Page Program - Uniform 4K-byte Sector Erase - Uniform 32K/64K-byte Block Erase - Full Chip Erase - Hardware Controlled Locking of Protected Sectors by WP# Pin - One Time Programmable (OTP) Security Register - 3- 512 Byte Security Registers with OTP Lock - 128-bit Unique ID for each device - Fast Program and Erase Speed Typical - 30us Byte program time - 0.5ms Page program time - 50ms 4K-byte sector erase time - 0.16s 32K-byte block erase time - 0.3s 64K-byte block erase time - JEDEC Standard Manufacturer and Device ID Read Methodology - Ultra-Low Power Consumption Typical - 1u A Deep Power Down current - 15u A Standby current - 7.5m A Active Read current at 85MHz - 6m A Active Program or Erase current - High Reliability - 100,000 Program / Erase Cycles - 20-year Data Retention - Industry Standard Green Package Options - 8-Lead SOP...