PY25R128LA Overview
Key Features
- Standard SPI: SCLK, CS#, SI, SO
- Dual SPI: SCLK, CS#, IO0, IO1
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- DTR: Double Transfer Rate Read Flexible Architecture for Code and Data Storage
- Uniform 256-byte Page Program
- Uniform 4K-byte Sector Erase
- Uniform 32K/64K-byte Block Erase
- Full Chip Erase One Time Programmable (OTP) Security Register
- 3*1024-Byte Security Registers with OTP Lock 128-bit Unique ID for each device Support Replay Protection Monotonic Counter (RPMC)
- Four 32-bit Monotonic Counters
