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P4C1024L Datasheet PDF

Pyramid Semiconductor P4C1024L

The P4C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. The RAM operates from a single 5V±10% tolerance power supply.
Part No. P4C1024L
Datasheet P4C1024L Download
Manufacturer
Pyramid Semiconductor
Description LOW POWER 128K x 8 CMOS STATIC RAM
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P4C1024L datasheet page 1 preview

FEATURES

VCC Current (Commercial/Industrial) — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70 (Commercial or Industrial) Single 5 Volts ±10% Power Supply Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 600 mil Plastic and Ceramic DIP —32-Pin 445 mil SOP —32-Pin TSOP Easy Memory Expansion Using CE1, CE2 and OE Inputs

DESCRIPTION

Inputs are fully TTL-compatible. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW.
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