HYB18L512320BF-7.5
Overview
Features
4 banks × 4 Mbit × 32 organization (dual-die) Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequential or interleaved Programmable drive strength: full, 1/2, 1/4 and 1/8 Auto refresh and self refresh modes Refresh cycles:
- 8192 refresh cycles / 64 ms Auto precharge mercial (-0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range Package:
- Dual-Die 90-ball PG-TFBGA package (13.0 × 8.0 × 1.2 mm) Ro HS pliant Products1)
Power Saving Features
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- Low supply voltages: VDD = 1.70 V to 1.95 V, VDDQ = 1.70 V to 1.95 V Optimized self refresh (IDD6) and standby currents (IDD2 / IDD3) Programmable Partial Array Self Refresh (PASR) Temperature pensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Power-Down and Deep Power Down modes
TABLE 1
Performance
Part Number Speed Code Speed Grade...
