HYB18T256161BF-28 Overview
1.20 Internet Data Sheet .. HYB18T256161BF 20/25/28 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256161BF 20/25/28 Revision History: 1.20 Page All All 94-101 82-86 All Subjects (major changes since last revision) Typos corrected Final Data Sheet added chapter 7 explaining AC timing measurement condition (reference load.
HYB18T256161BF-28 Key Features
- Data masks (DM) for write data
- 1.8 V ± 0.1V VDD for [-20/-25/-28]
- 1.8 V ± 0.1V VDDQ for [-20/-25/-28]
- Posted CAS by programmable additive latency for better
- DRAM organizations with 16 data in/outputs mand and data bus efficiency
- Double Data Rate architecture
- Off-Chip-Driver impedance adjustment (OCD) and On- two data transfers per clock cycle Die-Termination (ODT) for better s
- four internal banks for concurrent operation
- Auto-Precharge operation for read and write bursts
- Programmable CAS Latency: 3, 4, 5, 6, 7
HYB18T256161BF-28 Applications
- Data masks (DM) for write data
- 1.8 V ± 0.1V VDD for [-20/-25/-28]
- 1.8 V ± 0.1V VDDQ for [-20/-25/-28]
- Posted CAS by programmable additive latency for better
- DRAM organizations with 16 data in/outputs mand and data bus efficiency