HYB18T512161B2F-25 Overview
1.1 Internet Data Sheet .. HYB18T512161B2F 20/25 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161B2F 20/25 Revision History: 1.1 Page All Subjects (major changes since last revision) Typo Changes We Listen to Your ments Any information within this document that you feel is wrong, unclear or missing at all?
HYB18T512161B2F-25 Key Features
- Data masks (DM) for write data
- 1.8 V ± 0.1V VDD for [-20/-25]
- 1.8 V ± 0.1V VDDQ for [-20/-25]
- Posted CAS by programmable additive latency for better
- DRAM organizations with 16 data in/outputs mand and data bus efficiency
- Double Data Rate architecture
- Off-Chip-Driver impedance adjustment (OCD) and On- two data transfers per clock cycle Die-Termination (ODT) for better s
- four internal banks for concurrent operation
- Auto-Precharge operation for read and write bursts
- Programmable CAS Latency: 3, 4, 5, 6, 7