HYB18T512161B2F-25 Product details
This page provides the datasheet information for the HYB18T512161B2F-25, a member of the HYB18T512161B2F-20 512-Mbit x16 DDR2 SDRAM family.
Description
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling).
Features
- The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
- Data masks (DM) for write data.
- 1.8 V ± 0.1V VDD for [.
- 20/.
- 25].
- 1.8 V ± 0.1V VDDQ for [.
- 20/.
- 25].
- Posted CAS by programmable additive latency for better.
- DRAM organizations with 16 data in/outputs command and data bus efficiency.
- Double Data Rate architecture:.
- Off-Chip-Driver impedance adjustment (OCD) and On.
- two data.
HYB18T512161B2F-25 Datasheet