HYE18L512160BF-7.5 Datasheet | Qimonda AG

Overview Features 4 banks × 8 Mbit × 16 organization Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequential or interleaved Programmable drive strength Auto refresh and self refresh modes 8192 refresh cycles / 64 ms Auto precharge mercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range Dual-Die 54-ball PG-TFBGA package (12.0 × 8.0 × 1.2 mm) Ro HS pliant Products1) Power Saving Features - - - - - Low supply voltages: VDD = 1.70 V to 1.95 V, VDDQ = 1.70 V to 1.95 V Optimized self refresh (IDD6) and standby currents (IDD2 / IDD3) Programmable Partial Array Self Refresh (PASR) Temperature pensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Power-Down and Deep Power Down modes TABLE 1 Performance Part Number Speed Code Speed Grade Access Time (t ACmax) Clock Cycle Time (t CKmin) CL = 3 CL = 2 CL =...