Datasheet Details
| Part number | HYS72T32000HP |
|---|---|
| Manufacturer | Qimonda AG |
| File Size | 1.04 MB |
| Description | 240-Pin Registered DDR2 SDRAM Modules |
| Datasheet |
 HYS72T32000HP Datasheet
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General Description
devices and a PLL for the clock distribution.
This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing.
Decoupling capacitors are mounted on the PCB board.
Key Features
- Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type.
- Auto Refresh (CBR) and Self Refresh.
- Average Refresh Period 7.8 µs at a T lower than 85 °C, 3.9 µs between 85 °C and 95 °C.
- Programmable self refresh rate via EMRS2 setting.
- All inputs and outputs SSTL_18 compatible.
- Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT).
- Serial Presence Detect with E2PROM.
- Based on standard refer.
