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HYS72T64001HR - 240-Pin Registered DDR2 SDRAM Modules

This page provides the datasheet information for the HYS72T64001HR, a member of the HYS72T32000HR 240-Pin Registered DDR2 SDRAM Modules family.

Datasheet Summary

Description

devices and a PLL for the clock distribution.

This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing.

Decoupling capacitors are mounted on the PCB board.

Features

  • Programmable CAS Latencies (3, 4, 5 & 6), Burst Length (4 & 8) and Burst Type.
  • Auto Refresh (CBR) and Self Refresh.
  • All inputs and outputs SSTL_18 compatible.
  • Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT).
  • Serial Presence Detect with E2PROM.
  • RDIMM Dimensions (nominal): 30 mm high, 133.35 mm wide.
  • Based on Standard reference layouts Raw Card “A-F”, “BG” & “C-H”.
  • RoHS compliant products1).

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Datasheet Details

Part number HYS72T64001HR
Manufacturer Qimonda AG
File Size 3.86 MB
Description 240-Pin Registered DDR2 SDRAM Modules
Datasheet download datasheet HYS72T64001HR Datasheet
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March 2007 www.DataSheet4U.com HYS72T32000HR–[2.5/3/3S/3.7/5]–A HYS72T64001HR–[2.5/3/3S/3.7/5]–A HYS72T64020HR–[2.5/3/3S/3.7/5]–A 240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHS Compliant Internet Data Sheet Rev. 1.21 Internet Data Sheet www.DataSheet4U.com HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A Registered DDR2 SDRAM Modules HYS72T32000HR–[2.5/3/3S/3.7/5]–A, HYS72T64001HR–[2.5/3/3S/3.7/5]–A, HYS72T64020HR–[2.5/3/3S/3.7/5]–A Revision History: 2007-03, Rev. 1.21 Page All All Chapter 4 Chapter 5 Subjects (major changes since last revision) Qimonda update Adapted internet edition SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types Package Outlines updated Previous Revision: 2005-09, Rev. 1.2 Previous Revision: 2005-06, Rev. 1.
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