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HYB18T256160BF - 256-Mbit Double-Data-Rate-Two SDRAM

General Description

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and CK falling).

Key Features

  • The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
  • Off-Chip-Driver impedance adjustment (OCD) and.
  • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality.
  • DRAM organizations with 4, 8 and 16 data in/outputs.
  • Auto-Precharge operation for read and write bursts.
  • Double Data Rate architecture: two data transfers per.
  • Auto-Refresh, Self-Refresh and power saving.

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Datasheet Details

Part number HYB18T256160BF
Manufacturer Qimonda
File Size 4.11 MB
Description 256-Mbit Double-Data-Rate-Two SDRAM
Datasheet download datasheet HYB18T256160BF Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History: 2007-07, Rev. 1.11 Page All All Subjects (major changes since last revision) Adapted Internet edition. Editorial change Added product types with industrial temperature Previous Revision: 2006-12, Rev. 1.00 Previous Revision: 2007-05, Rev. 1.