HYB18T512400B Description
1.1 Internet Data Sheet HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512400B[C/F], HYB18T512160B[C/F], HYB18T512800B[C/F] Revision History: 1.1 Page All All All Subjects (major changes since last revision) Adapted internet edition Added more product types Qimonda template update Previous Revision: We Listen to Your ments Any information within this document that you feel is wrong, unclear or...
HYB18T512400B Key Features
- Off-Chip-Driver impedance adjustment (OCD) and On- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O Die-Te
- DRAM organizations with 4 and 8 data in/outputs
- Auto-Precharge operation for read and write bursts
- Double-Data-Rate-Two architecture: two data transfers
- Auto-Refresh, Self-Refresh and power saving Powerper clock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable Burst Length: 4 and 8 85 °C, 3.9 µs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting