HYB18TC256160AF Overview
2007-11-23 Internet Data Sheet HY[B/I]18TC256[80/16]0AF 256-Mbit Double-Data-Rate-Two SDRAM Revision History: 1.3, 2007-11 All All 98 .. Adapted internet edition Added more products Corrected tRP in tables in chapter 7.2 Previous Revision:.
HYB18TC256160AF Key Features
- Off-Chip-Driver impedance adjustment (OCD) and
- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O On-Die-Termination (ODT) for better signal quality
- DRAM organizations with 8,16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 μs at a TCASE lower
- Programmable Burst Length: 4 and 8 than 85 °C, 3.9 μs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting