HYB18TC256800AF - 256-Mbit Double-Data-Rate-Two SDRAM

This page provides the datasheet information for the HYB18TC256800AF, a member of the HYB18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM family.

Product Overview

Qimonda

Part number	HYB18TC256800AF
Manufacturer	Qimonda
File Size	3.45 MB
Description	256-Mbit Double-Data-Rate-Two SDRAM
Datasheet	HYB18TC256800AF Datasheet
Additional preview pages of the HYB18TC256800AF datasheet.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and CK falling).

The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
Off-Chip-Driver impedance adjustment (OCD) and.
1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality.
DRAM organizations with 8,16 data in/outputs.
Auto-Precharge operation for read and write bursts.
Double Data Rate architecture: two data transfers per.
Auto-Refresh, Self-Refresh and power saving Powerc.

Other Datasheets by Qimonda

Published: Sep 10, 2008 |