Datasheet Details
| Part number | HYB25D512400BF |
|---|---|
| Manufacturer | Qimonda |
| File Size | 768.99 KB |
| Description | 512-Mbit Double-Data-Rate SDRAM |
| Datasheet |
 HYB25D512400BF Datasheet
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General Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
It is internally configured as a quad-bank DRAM.
The 512-Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation.
Key Features
- Double data rate architecture: two data transfers per clock cycle.
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
- DQS is edge-aligned with data for reads and is center-aligned with data for writes.
- Differential clock inputs (CK and CK).
- Four internal banks for concurrent operation.
- Data mask (DM) for write data.
- DLL aligns DQ and DQS transitions with CK transitio.
