HYB25D512400BF
Overview
HYB25D512[40/16/80]0B[E/F/C/T](L) Double-Data-Rate SDRAM
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics
Features
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is center-aligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst Lengths: 2, 4, or 8
- CAS Latency: (1.5), 2, 2.5, 3
- Auto Pre charge option for each burst access
- Auto Refresh and Self Refresh Modes
- RAS-lockout supported t RAP=t RCD
- 7.8 µs Maximum Average Periodic Refresh Interval
- 2.5 V (SSTL_2...
