HYB25DC256163CE-4
Overview
HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM
This chapter lists all main features of the product family HYB25DC256163CE and the ordering information.
1.1 Features
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is center-aligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst Lengths: 2, 4, or 8
- CAS Latency: 3
- Auto Precharge option for each burst access
- Auto Refresh and Self Refresh Modes
- 7.8 µs Maximum Average Periodic Refresh Interval
- 2.5 V (SSTL_2 patible) I/O
- VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V...
