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HYB39S128160FEL - 128-MBit Synchronous DRAM

Download the HYB39S128160FEL datasheet PDF. This datasheet also covers the HYB39S128160FE variant, as both devices belong to the same 128-mbit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively.

Key Features

  • Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: P(G).
  • TSOPII.
  • 54 400 mil width This chapter lists all main features of the product family HY[B/I]39.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB39S128160FE_Qimonda.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYB39S128160FEL
Manufacturer Qimonda
File Size 1.39 MB
Description 128-MBit Synchronous DRAM
Datasheet download datasheet HYB39S128160FEL Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HYB39S128160CT 128-MBit Synchronous DRAM Infineon Technologies
HYB39S128160CTL 128-MBit Synchronous DRAM Infineon Technologies
HYB39S128400CT 128-MBit Synchronous DRAM Infineon Technologies
HYB39S128400CTL 128-MBit Synchronous DRAM Infineon Technologies
HYB39S128800CT 128-MBit Synchronous DRAM Infineon Technologies

Other Datasheets by Qimonda

Part Number Description
HYB39S128160FE 128-MBit Synchronous DRAM
HYB39S128160FT 128-MBit Synchronous DRAM
HYB39S128160FTL 128-MBit Synchronous DRAM
HYB39S128400FE 128-MBit Synchronous DRAM
HYB39S128400FEL 128-MBit Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
October 2007 www.DataSheet4U.com HYB39S128400F[E/T](L) HY[B/I]39S128800F[E/T](L) HY[B/I]39S128160F[E/T](L) HYB39S 128407 F E 128-MBit Synchronous DRAM Green Product SDRAM Data Sheet Rev. 1.32 Data Sheet www.DataSheet4U.com HY[B/I]39S128[40/80/16][0/7]F[E/T](L) 128-MBit Synchronous DRAM HYB39S128400F[E/T](L), HY[B/I]39S128800F[E/T](L), HY[B/I]39S128160F[E/T](L) Revision History: 2007-10, Rev. 1.32 Page All 23 13 15 19 19 22 22 15 21 22 4 Subjects (major changes since last revision) Adapted Internet Version Corrected number of refresh cycles Corrected operation command "Power Down / Clock suspend ...” in truth table Corrected text to "After the mode register is set a NOP command is required" Corrected text to "One clock delay is required for mode entry and exit", chapter 3.