HYS72T512022EP-3.7-B Overview
loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board.
HYS72T512022EP-3.7-B Key Features
- 240-Pin PC2-5300 and PC2-4200 DDR2 SDRAM memory modules
- 512M ×72 module organization and 2 × 256M × 4 chip organization
- Registered DIMM Parity bit for address and control bus
- 4GB modules built with 1Gbit DDR2 SDRAMs in P-TFBGA-71 chipsize packages
- Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply
- Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4 & 8) and Burst Type
- Auto Refresh (CBR) and Self Refresh