HYS72T512341HHP-3.7-B Overview
1.0 Internet Data Sheet .. 1.0 Page All All All Chapter 4 Subjects (major changes since last revision) Qimonda update Adapted internet edition Added HYS672T512341HJP-[3.7/5]-B and HYS72T512341HKP-[3.7/5]-B modules SPD codes updated Previous Revision: 0.5 We Listen to Your ments Any information within this document that you feel is wrong, unclear or missing at all?
HYS72T512341HHP-3.7-B Key Features
- 240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules
- Four rank 512M ×72 module organization, and 512M ×4 chip organization
- Registered DIMM Parity bit for address and control bus
- Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply
- Programmable CAS Latencies (3, 4, 5), Burst Length (4 & 8) and Burst Type
- Auto Refresh (CBR) and Self Refresh
- MHz MHz MHz ns ns ns ns