HYS72T512422HFN-3.7-A
Overview
Features
- Detects errors on the channel and reports them to the host memory controller.
- Automatic DDR2 DRAM Bus Calibration.
- Automatic Channel Calibration.
- Full Host Control of the DDR2 DRAMs.
- Over-Temperature Detection and Alert.
- Hot Add-on and Hot Remove Capability.
- MBIST and IBIST Test Functions.
- Transparent Mode for DRAM Test Support.
- Low profile: 133.35mm x 30.35 mm
- 240 Pin gold plated card connector with 1.00mm contact centers (JEDEC standard pending).
- Based on JEDEC standard reference card designs (Jedec standard pending).
- SPD (Serial Presence Detect) with 256 Byte serial E2PROM.
- Ro HS pliant Products1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
- 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications.
- Module organisation two ranks 512M ×72
- JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with...
