V7001
Key Features
- JEDEC standard SDR-SDRAM supported
- Transaction pipeline for maximum utilization of the Memory Bus
- 3 Request buffers for transaction pipeline
- Supports CAS latencies of 1, 2 and 3
- 4 or 8 beat burst transactions supported
- Supports up to 4 chip selects of Memory devices
- Page mode support for up to 16 open pages
- Supports flexible Row and Column addressing
- Supports up to 4GB of Memory Address space
- Supports Registered DIMM Mode
