Qualcore V7001
The configuration bus facilitates to program the internal SDR configuration registers. This bus width is same as the memory data bus width.| Part No. | V7001 |
|---|---|
| Datasheet | V7001 Download |
| Manufacturer | Qualcore |
| Description | SDR-SDRAM Memory Controller |
| Buy | Stock & Price |
FEATURES
● JEDEC standard SDR-SDRAM supported● Transaction pipeline for maximum utilization of the Memory Bus
● 3 Request buffers for transaction pipeline
● Supports CAS latencies of 1, 2 and 3
● 4 or 8 beat burst transactions supported
● Supports up to 4 chip selects of Memory devices
● Page mode support for up to 16 open pages
● Supports flexible Row and Column addressing
● Supports up to 4GB of Memory Address space
● Supports Registered DIMM Mode
● Supports Auto Refresh and Self Refresh
● Refresh for populated banks only
● Automatic Refresh of idle slots
● Interrupt generation for invalid address requests
● Programmable Refresh rate
● Programmable timing parameters
● Configuration register read/ write interface fully complies with standard OCP Slave (basic signals)
● Configurable 8/16/32/64-bit OCP Slave interface for register configuration
● Configurable 8/16/32/64-bit memory data bus interface for data transfers Functional Overview SDR is a very high performance memory controller to interface with SDR-SDRAM memory devices.
