| Part number | QL3040 |
|---|---|
| Datasheet | QL3040_QuickLogicCorporation.pdf |
| File Size | 481.36 KB |
| Manufacturer | QuickLogic Corporation |
| Description | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
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QL3040 pASIC 3 FPGA Data Sheet 40,000 Usable PLD Gate pASIC 3 FPGA bining High Performance and High Density Device Highlights High Performance & High Density 40,000 Usable PLD Gates with 252 I/Os 300 MHz 16-bit .. Eight Low-Skew Distributed Networks Two array clock/control networks available Counters, 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast...
See all QuickLogic Corporation datasheets
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|---|---|
| QL3004 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3004E | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3006 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3025 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3060 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
