QL1P075 Overview
Enter VLP mode from normal operation in less than 250 µs Exit from VLP mode to normal operation in less than 250 µs Embedded Dual Port SRAM Up to eight dual-port 4-kilobit high performance SRAM blocks Embedded synchronous/asynchronous FIFO controller Configurable and cascadable aspect ratio Security Links There are several security links to disable JTAG access to the device. Programming these optional links pletely...