QL4009 - Quick RAM

Pin TDI/RSI TRSTB/RRO TMS TCK TDO/RCO STM I/ACLK I/GCLK I I/O VCC VCCIO GND GND/THERM Function Test Data In for JTAG / RAM init.

Serial Data In Active low Reset for JTAG / RAM init.

reset out Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG / RAM init.

• up to 16 simultaneous inputs and 5 outs within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines (see Figure 4). High Performance s s s s Input + logic cell + output total delays under 6 ns Data path speeds over 400 MHz counter speeds over 300 MHz FIFO speeds over 160 MHz QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 AZ OZ WDATA WADDR RAM Module (1,152 bits) RDATA RADDR QZ NZ FZ.