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V360EPC Datasheet PDF

QuickLogic V360EPC

V360EPC is also a suitable candidate for a variety of high-performance applications based on Motorola, IBM, DEC and Hitachi embedded processors - where a minimal amount of glue logic is needed. V360EPC is the second generation of V3’s I2O ready PCI bridges - fully backward compatible with V962PBC and V292PBC Rev B2 devices and is supporting powerful features like Hot Swap and DMA chaining. The PCI bus can be run at full 33MHz, independent of local bus clock rate.
Part No. V360EPC
Datasheet V360EPC Download
Manufacturer
QuickLogic
Description Local Bus to PCI Bridge
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V360EPC datasheet page 1 preview

DESCRIPTION

and Pinout Table 2 below lists the pin types found on the V360EPC. Table 3 describes the function of each pin on the V360EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package. Table 2: Pin Types Pin Type PCI I PCI O PCI I/O PCI I/OD I/O4 I O4 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 4mA output drive. TTL input only pin. TTL output pin with 4mA output drive.

DESCRIPTION

2 V360EPC Data Sheet Rev 1.2 Copyright © 1998, V3 Semiconductor Inc. V360EPC Table 3: Signal Descriptions PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME Type PCI I/O PCI I/O PCI I/O PCI I/O Ra Z Z Z Z

DESCRIPTION

Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0]
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