VRS51L3074 Overview
SPI INTERFACE OVERVIEW 4 SPICS[1:0] 2 SPICLKPH 1 0 SPICLKPOL SPIMASTER Before the SPI can be accessed it must first be enabled by setting the SPIEN bit of the PERIPHEN1 register to 1. When the SPIMASTER bit is set to 1, the SPI interface operates in master mode. This is the default operating mode of the VRS51L3074 SPI interface after reset.
VRS51L3074 Key Features
- Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to fo
- SPICTRL SFR C1H
- Arrows indicate the edge where the data acquisition occurs
- Arrows indicate the edge where the data acquisition occurs