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VRS51L3074 - FRAM-enhanced high performance 8051-based microcontroller coupled

Datasheet Summary

Description

SPI Communication Speed (Master Mode) 000 = Sys Clk / 2 ( / 8 if SPISLOW = 1) 001 = Sys Clk / 4 ( / 16 if SPISLOW = 1) 010 = Sys Clk / 8 ( / 32 if SPISLOW = 1) 011 = Sys Clk / 16 ( / 64 if SPISLOW = 1) 100 = Sys Clk / 32 ( / 128 if SPISLOW = 1) 101 = Sys Clk / 64 ( / 256 if SPISLOW = 1) 110 = Sys Cl

Features

  • include:.
  • Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals 9.1 SPI Control Registers The.

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Datasheet Details

Part number VRS51L3074
Manufacturer Ramtron Corporation
File Size 2.03 MB
Description FRAM-enhanced high performance 8051-based microcontroller coupled
Datasheet download datasheet VRS51L3074 Datasheet
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www.DataSheet4U.com VRS51L3074 9 SPI Interface The SPI interface of the VRS51L3074’s provides numerous enhancements compared to other vendor offerings. The SPI interface’s key features include: • • • • • • • • Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals 9.1 SPI Control Registers The SPICTRL register controls the operating modes of the SPI interface in master mode.
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