VRS51L3074 Datasheet PDF

Ramtron VRS51L3074

the VRS51L3074’s provides numerous enhancements compared to other vendor offerings. The SPI interface’s key features include: • • • • • • • • Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals 9.1 SPI Control Registers The SPICTRL register controls the operating modes of the SPI interface in master mode. When the SPIMASTER bit is set to 1, the SPI interface operates in master mode.