RTL8306 Datasheet | Realtek

Features n n n Support eight/six 10/100Mbps Ethernet ports with RMII interface Provided non-blocking and non-head-of-lineblocking forwarding 50MHz 2M bits DRAM is built in as packet storage buffer. Page based buffer management to efficiently utilize the internal packet buffer Ultra low power consumption with less than 180m A at 3.3V operating voltage Embedded 16K entries of look-up table and 128 entries of CAM Support address hashing or direct mapping for look-up table. 128-entry CAM is used to eliminate the hash collision problem Support full and half duplex operations n n Link, speed and duplex status are autodetected via MDIO Flow control fully supported: l l Half-duplex: back pressure Full-duplex: IEEE 802.3X n n n n n n n n n n Auto-negotiated Full-duplex flow control by writing the ability via MDIO to external PHY Support store-and-forward and cut-through Provide a LED display especially to indicate a network loop existence Broadcast storm control Reversible PHYAD order for diverse PHY 24C02 interface 128-pin PQFP, 0.35 um, 3.3V CMOS technology n 99/10/26 Datasheet pdf - http://..net/ 8308/8306 Preliminary Product Specification Subject to change 2. General Description The RTL8308/8306 provides eight/six 10/100 Mbps RMII Ethernet ports. Each port can operate in 10 Mbps or 100 Mbps data rate, and in full or half duplex mode. Speed, duplex and link status can be acquired by periodically polling the status of the PHY devices via MDIO. 2M ( or 32K x 64 ) bits, or 256K bytes DRAM operating in 50MHz clock is built-in as packet storage buffer. To efficiently utilize the packet buffer, the RTL8308/8306 divides the 256K bytes DRAM into 1K pages of storage spaces, i.e., per page contains 256 bytes. For Ethernet packets, the maximum of seven pages are used and the minimum is one. Address look-up table consists of two spaces. One is a 16K entries of hash table and another is a 128 entries of CAM. The RTL8308/8306 uses address hashing algorithm or direct mapping...