FEATURES
Supports eight 10/100Mbps Ethernet ports with RMII interface Provides forwarding of non-blocking and non-head-of-line-blocking 2M bit DRAM built in as a packet storage buffer Page based buffer management to efficiently utilize the internal packet buffer Ultra low power consumption with less than 160mA at 3.3V operating voltage Embedded 8K entry look-up table and 128 entry CAM Supports address hashing or direct mapping for look-up table 128-entry CAM is used to eliminate the hash collision issues Supports full and half duplex operation Link, speed and duplex status are auto-detected via MDIO RTL8308B Broadcast storm control Flow control fully supported: Half-duplex: back pressure Full-duplex: IEEE 802.3X Auto-negotiated Full-duplex flow control by writing the ability via MDIO to external PHY Supports Store-and-forward and cut-through operation Provides an LED display to indicate network loop existence Reversible PHYAD order for diverse PHY usage 3.3V 24LC02 interface Optional EEPROM 24LC02 for Loop detect configuration 128-pin PQFP, 0.35 um, 3.3V CMOS technology 2002/01/23 2 Rev.
Realtek
