RTL8801B Datasheet PDF

Realtek RTL8801B

The RTL8801B provides a two-port physical layer (PHY) function in a cable-based IEEE 1394-1995 and IEEE P1394a network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.

Part No.	RTL8801B
Datasheet	RTL8801B Download
Manufacturer	Realtek
Description	2-Port Cable Transceiver / Arbiter Chip
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GENERAL DESCRIPTION

1. Data bits to be transmitted through the cable ports are received from the Link On 2/4/8 data lines (D0-D8), and are latched internally in the RTL8801B in synchronization with the 49.152MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216Mbps as an outbound data-strobe information stream. During transmission, the encoded data is transmitted on the twisted pair B (TPB) cable pair(s), and the encoded strobe information is transmitted on the twisted pair A (TPA) cable pair(s). 2. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the received clock signal and the serial data bits. The serial data bits are split into two nibbles, or four by two bits, and parallel transmitted (repeated) out of the other active (connected) cable ports.