HD49335NP Datasheet | Renesas

Description The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. .. if examining There are address map and timing generator charts besides this specification. May be contacted to our sales department the details. Functions - - - - - - - Correlated double sampling PGA Serial interface control 10-bit ADC Timing generator Operates using only the 3 V voltage Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 220 m W (Typ), maximum frequency: 36 MHz (HD49335HNP) Power dissipation: 150 m W (Typ), maximum frequency: 25 MHz (HD49335NP) - ADC direct input mode - QFN 64-pin package Features - Suppresses low-frequency noise, which output from CCD by the correlated double sampling. - The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. - High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier. - PGA, pulse timing, standby mode, etc., is achieved via a serial interface. - High precision is provided by a 10-bit-resolution A/D converter. - Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization (wave pattern). It is patented by Renesas. - Timing generator generates the all of pulse which are needed for CCD driving. Rev.1.0, Feb.12.2004, page 1 of 29 HD49335NP/HNP Pin Arrangement VRM VRT VRB BIAS ADC_in AVSS DVSS3 STROB SUB_PD SUB_SW XSUB CH4 CH3 CH2 CH1 XV4 .. AVDD BLKC CDS_in AVDD BLKFB BLKSH AVSS Test2 Test1 DLL_C DVDD1 MON 41cont CS SDATA SCK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 23 58 22 59 21 60 20 61 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ID DVSS1,2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DVDD2 DVSS3 CLK_in HD_in...