HD49340HNP Datasheet | Renesas

Description The HD49340NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip. .. Functions - - - - - - - Correlated double sampling PGA Offset pensation Serial interface control 10-bit ADC Operates using only the 3 V voltage Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 120 m W (Typ), maximum frequency: 36 MHz (HD49340HNP) Power dissipation: 60 m W (Typ), maximum frequency: 25 MHz (HD49340NP) - ADC direct input mode - QFN 36-pin package Features - Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling. - The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. - High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier. - Feedback is used to pensate and reduce the DC offsets including the output DC offset due to PGA gain change and the CCD offset in the CDS (correlated double sampling) amplifier input. - PGA, standby mode, etc., is achieved via a serial interface. - High precision is provided by a 10-bit-resolution A/D converter. Rev.1.0 Apr 20, 2004 page 1 of 21 HD49340NP/HNP Pin Arrangement ADCIN AVSS AVDD BIAS BLKC CDSIN BLKFB BLKSH AVDD .. VRM VRT VRB DVDD DVSS CS SDATA SCK D0 27 26 25 24 23 22 21 20 19 28 18 29 17 30 16 31 15 32 14 33 13 34 12 35 11 36 10 1 2 3 4 5 6 7 8 9 D1 D2 D3 D4 D5 D6 D7 D8 D9 (Top view) AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD Pin Description Pin No. 1 to 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol D0 to D9 DRDVDD DVSS ADCLK DVDD PBLK OBP SPBLK SPSIG AVSS AVDD BLKSH BLKFB CDSIN BLKC BIAS AVDD AVSS ADCIN VRM VRT VRB Description Digital output Output buffer power supply (3 V) Digital ground (0 V) ADC conversion clock input pin Digital power supply (3 V) Preblanking input pin...