HD74LS165A Datasheet | Renesas

feature gated clock inputs and plementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is acplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs. Features - Ordering Information Part Name HD74LS165AP HD74LS165AFPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) - EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement Shift/ Load Clock E Parallel Inputs F G H Output QH GND 1 2 3 4 5 6 7 8 Shift/Load Clock CK Inhibit E F G H QH D C B A Serial QH Input 16 15 14 13 12 11 10 9 VCC Clock Inhibit D C B A Serial Input Output QH Parallel Inputs (Top view) Rev.3.00, Jul.15.2005, page 1 of 7 Function Table Inputs Shift / Load L H H H H Clock Inhibit X L L L H Clock X ↑ ↑ ↑ X Serial X X H L X Parallel A…H a…h X X X X Internal outputs QA a QA0 H L QA0 QB b QB0 QAn QAn QB0 Output QH h QH0 QGn QGn QH0 Notes: 1. H; high level, L; low level, X; irrelevant 2. ↑; transition from low to high level 3. a to h; the level of steady-state input at inputs A to H respectively 4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established. 5. QAn to QGn; the level of QA to QG,...