M65881AFP Datasheet | Renesas

.. Digital Amplifier Processor of S-Master- Technology DESCRIPTION REJ03F0004-0100Z Rev.1.00 2003.05.08 The M65881AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing. The M65881AFP has built-in 24bit sampling rate converter and digital-gain-controller. The M65881AFP enables to realize high precise ( X`tal oscillation accuracy.) full digital amplifier systems bining with power driver IC. Features - Built-in 24bit Sampling Rate Converter. Input Signal Sampling Rate from 32KHz to 192KHz (24bit Maximum). 4 kinds of Digital Input Format. - Built-in L/R Independent Digital Gain Control. - Built-in Soft Mute Function with Exponential Approximate-Curve. - Correspondence to Output for Headphone. OUTLINE : 42P2R 0.8mm pitch 42pin SSOP MAIN SPECIFICATION - Master Clock Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso - Input Signal Format: MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit) LSB First Right Justified(24bit),I2S(24bit) - Input Signal Sampling Rate from 32k Hz to 192k Hz. - Gain Control Function: +30d B~-∞d B (0.1d B Step until -96d B, -138d B Minimum) - Third Order ∆Σ (16Fso:6bit/5bit,32Fso:5bit) APPLICATION DVD Receiver, AV Amplifier REMENDED OPERATING CONDITIONS Logic Block:1.8V±10%,PWM Buffer Block :3.3V±10% SYSTEM BLOCK DIAGRAM) M65881AFP Stream Power Driver ∆Σ PWM Stream Power Driver LC Filter 24bit CD DVD Audio etc. LRCK BCK DATA Sampling Rate Converter 32k Hz to 192k Hz LC Filter Level Control +30d B to -∞ 256fsi/512fsi Clock MCU...