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M6MGD13TW66CWG-P - CMOS FLASH MEMORY

General Description

The M6MGD13TW66CWG-P is a Stacked Chip Scale Package (S-CSP) that contents 128M-bit Flash memory and 64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded solder ball.

Key Features

  • Access Time Random Access/ Page Access Flash Mobile RAM Supply Voltage 70ns /25ns (Max. ) 85ns /25ns (Max. ) FM-VCC=2.7 ~ 3.0V Ta= -40 ~ 85 degree 72pin S-CSP, Ball pitch 0.80mm Outer-ball:Sn-Pb Ambient Temperature 64M-bit Mobile RAM is a 4,194,304 words high density RAM Package fabricated by CMOS technology for the peripheral circuit and DRAM cell for the memory array. The interface is compatible to an asynchronous SRAM. The cells are automatically refreshed and the refresh control is Applicatio.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Preliminary Notice: This is not a final specification. Some parametric limits are subject to change. Renesas LSIs M6MGD13TW66CWG-P 134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY & 67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM Stacked-CSP ( Chip Scale Package) Description The M6MGD13TW66CWG-P is a Stacked Chip Scale Package (S-CSP) that contents 128M-bit Flash memory and 64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded solder ball. 128M-bit Flash memory is a 8,388,608 words, single power supply and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR IV (Divided bit-line NOR IV) architecture for the memory cell.