621S Datasheet PDF - Renesas Low Skew 1 to 4 Clock Buffer Specs

621S - Low Skew 1 to 4 Clock Buffer

Datasheet Summary

Description

The 621S is a low cost, high-speed single input to four output clock buffer.

The 621S has best in class Additive Phase Jitter of sub 50fsec.

IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks.

Features

Low additive phase jitter RMS: 50fs.
Extremely low skew outputs (50ps).
Low cost clock buffer.
Packaged in 8-pin SOIC and 8-pin DFN, Pb-free.
Input/Output clock frequency up to 200 MHz.
Non-inverting output clock.
Ideal for networking clocks.
Operating Voltages: 1.8V to 3.3V.
Output Enable mode tri-states outputs.
Advanced, low power CMOS process.
Extended temperature range (-40°C to +105°C) Bloc.

Datasheet Details

Part number	621S
Manufacturer	Renesas
File Size	377.33 KB
Description	Low Skew 1 to 4 Clock Buffer
Datasheet	621S Datasheet
Additional preview pages of the 621S datasheet.

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Full PDF Text Transcription

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Low Skew 1 to 4 Clock Buffer 621S DATASHEET Description The 621S is a low cost, high-speed single input to four output clock buffer. The 621S has best in class Additive Phase Jitter of sub 50fsec. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact IDT for all of your clocking needs. Features • Low additive phase jitter RMS: 50fs • Extremely low skew outputs (50ps) • Low cost clock buffer • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free • Input/Output clock frequency up to 200 MHz • Non-inverting output clock • Ideal for networking clocks • Operating Voltages: 1.8V to 3.

Published: Jun 12, 2024 |