7028 Datasheet | Renesas

Features - True Dual-Ported memory cells which allow simultaneous reads of the same memory location - High-speed access - mercial: 15ns (max.) - Industrial: 20ns (max.) - Low-power operation - IDT7028L Active: 1W (typ.) Standby: 1m W (typ.) - Dual chip enables allow for depth expansion without external logic - IDT7028 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device Functional Block Diagram R/WL UBL CE0L CE1L - M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave - Interrupt Flag - On-chip port arbitration logic - Full on-chip hardware support of semaphore signaling between ports - Fully asynchronous operation from either port - Separate upper-byte and lower-byte controls for multi- plexed bus and bus matching patibility - TTL-patible, single 5V (±10%) power supply - Available in a 100-pin TQFP - Industrial temperature range (- 40°C to +85°C) is available for selected speeds - Green parts available, see ordering information R/WR UBR CE0R CE1R I/O 8-15L I/O 0-7L BUSYL(1,2) I/O Control I/O Control A15L A0L Address Decoder 64Kx16 MEMORY ARRAY 7028 CE0L CE1L OEL R/WL ARBITRATION INTERRUPT SEMAPHORE...